15
LTC4221
4221fa
generate a logic high output to indicate that V
OUT
is valid.
An internal high-to-low glitch filter helps to prevent nega-
tive voltage transients on each FB pin from deasserting its
PWRGD. The relationship between glitch filter time and an
FB pin transient voltage is shown in Figure 4. Using the
functionality of the PWRGD1 pin, the LTC4221 can be
configured to do sequential power-up and power-down as
shown by the circuit in Figure 5. Referring back to Figure 3,
ON2 is held low until V
OUT1
ramps high enough for FB1 to
exceed its undervoltage threshold at time point 5 when
PWRGD1 ramps up, pulling ON2 high. At time point 7, the
control logic sees ON2 exceeding its off threshold and so
commences a start-up cycle for channel 2. Similarly, when
ON1 is forced low by Q2 at time point 9, GATE1 is pulled
low by its 100糀 pull-down while ON2 is held high by the
R4 pull-up on PWRGD1. Its is only when channel 1 is
powered off and V
OUT1
discharges below its undervoltage
threshold at time point 10 that PWRGD1s internal
N-channel MOSFET pull-down is triggered and ON2 goes
low. At time point 11, ON2 trips its off threshold and
GATE2 pulls low with a 100糀 pull-down, powering off
channel 2.
For V
OUT
overvoltage detection, each FB pin has an over-
voltage comparator with a low-to-high threshold of 0.822V
and a low-to-high glitch filter of 18約. This threshold is
designed to be 33% higher than the undervoltage thresh-
old. If either FB pin trips this threshold, the fault latch is set,
all GATE pins are pulled low with internal NFET pull-downs
and the LTC4221 goes into a fault state.
In the third function, each FB pin is used to control its
channels current limit during its start-up cycle. This will
be featured in the Start-Up Cycle with Current Limit
section.
GATE Pin Functions
Each GATE pin controls the gate of its channels external
N-channel MOSFET. Individual internal charge pumps
powered by V
CC1
guarantee a gate drive of minimum 4.5V
and maximum 18V (internally clamped) for GATE1 and
GATE2. During UVLO, the internal charge pumps are off
and both GATE pins are pulled low by internal N-channel
MOSFET pull-downs. Outside UVLO, when ON1 is below
its off threshold, the charge pumps are on and GATE1 is
held low by an internal 100糀 current pull-down. Once
APPLICATIO S I FOR ATIO
U
U
U
+
V
CC1
ON1
SENSE1
ON2
PWRGD1
R
F2
15k
LTC4221*
GATE1
FB1
4221 F05
1
16
6
10
9
C
TIMER
1糉
GND
TIMER
R
F1
56k
V
OUT1
3.3V
5A
V
OUT2
2.5V
5A
Q1
IRF7413
R
SENSE1
0.004?/DIV>
C
LOAD1
Z1
Q2: 2N7002LT1
Z1: SMAJ10
* ADDITIONAL DETAILS
OMITTED FOR CLARITY
R
X1
10?/DIV>
C
X1
100nF
R4
10k
R2
2k
Q2
R1
10k
R6
10k
R5 10?/DIV>
R3 10k
LONG
V
CC1
LONG
PCB EDGE
CONNECTOR
(MALE)
SHORT
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
LONG
V
CC2
ON/OFF
Figure 5. Using PWRGD1 to Configure Sequential Power-Up/Power-Down
FEEDBACK TRANSIENT (mV)
40
60
80
20
50
70
30
10
0
0 20 40 60 80 100 120 140 160 180 200
4221 F04
T
A
= 25癈
Figure 4. FB Comparator Glitch Filter
Time vs Feedback Transient Voltage
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